Computers that are faster and consumer lesser and lesser amounts of energy would remain a disant dream, unless there is a technique that controls the all-important nanoscale strain in the processors, which remained difficult to observe thus far. However, now a new electron holography technique invented by researchers at the Centre d'élaboration de matériaux et d'études structurales (CEMES-CNRS) in Toulouse has made it possible to map deformation in a crystal lattice, with a precision and resolution unattained previously.

This new measurement device, which has been patented, overcomes almost all limitations of current methods, and should allow manufacturers to improve microprocessor production methods, and optimize future computers.

This work was published in the 19 June, 2008 issue of the journal Nature.

''Strained'' silicon forms a fundamental component of all recent microprocessors, as local strain-induced deformation in the crystal lattice enhances processor performance. The deformation greatly increases electron mobility, in the bargain boosting computer speed and reducing energy consumption.

However, as manufacturers could not analyse deformation accurately, they couldn't attain mastery of chip design, and essentially relied on simulations and performance monitoring, guessing in the dark without really knowing the strain state.

Using electron holography, the technique allows for the measurement of deformation such as compression, tension, and shear strain in numerous materials, with high precision and spatial resolution. Precision exceeds 0.1 per cent, or 0.5 picometers and spatial resolution is on the nanometer scale.  The real innovation as compared to traditional techniques is that it is allows for an analysis of larger areas, a micrometer rather than the previous 100 nanometers, with an unparalleled level of  precision.

The technique allows the study of samples that are ten times thicker than previous samples (300 nm), guaranteeing that observations are accurate. The thicker the sample, the less the strain is relaxed, and the closer the measured stain as compared to a real system. Measurements are taken directly, and not via simulations as done in other techniques.

This technique has been patented by CNRS in September 2007, and is most likely to be the method for measuring crystal lattice strain at the nanometer scale in the future, as it has the potential to optimise strain modelling in transistors and enhance their electrical efficiency.